Integrated circuit designs, such as those for modern system-on-a-chip (“SOC”) devices, continue to grow is size and complexity. Shrinking transistor sizes mean that more and more transistors can be included in a SOC, while a greater number of features or components can be packed on the SOC. Functional verification of such devices, which may be SOCs or any other type of integrated circuit fabricated on a single substrate or multiple interconnected substrates, is usually included as part of the circuit design flow to help ensure that the fabricated device functions as intended.
The increasing size and complexity of the circuit designs to be verified (devices under test, or “DUT”) mean that the functional verification portion of the design cycle is increasing in length. The verification stage may in some case be the longest stage of the design cycle. For example, running a simulation on a host computer to verify a SOC, or even a sub-portion of the SOC, written in the register transfer language (“RTL”) design abstraction may take anywhere from hours to days. Devices that perform simulation-acceleration (also known as co-simulation) in a verification flow (or methodology) leverage high-performance hardware emulators along with simulation to increase the speed of the verification stage.
After a gate-level or netlist of a SOC or other complex design has been created, the simulation times may become much longer and challenging to verify, especially once timing information is included. This timing data may be in Standard Delay Format (“SDF”), which currently is an IEEE standard for the representation and interpretation of timing data that may be applied in a design flow. SDF may contain sections for both delays in interconnect and cell delays. SDF may also be used to back annotate as well as forward annotate a netlist. In a netlist simulation, including those using SDF annotation, just the initialization/configuration phase for some SOCs or chips may be extremely time consuming, taking anywhere between hours and days, which is all before the actual circuit testing commences. The significant length of time and resources that may be used to proceed through this initialization/configuration phase with different configuration scenarios for each test presents a challenge for engineers who have time and resource constraints.
Current approaches to deal with the long initialization and configuration times generally perform one of two workarounds. The first is to only partially initialize and configure the SOC. However, this results in missing complete configuration of the SOC during gate-level netlist simulation with timing. The described embodiments provide a complete configuration. The second is to provide for back door access using functional verification simulators. However, by circumventing the interface with back door access there is no validation of the interface, which is not desirable.